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Quantified Decision Procedures & Interpolation f. Correction

Quantified Decision Procedures & Interpolation f. Correction

Roderick Bloem (ORCID: 0000-0002-1411-5744)
  • Grant DOI 10.55776/I774
  • Funding program Principal Investigator Projects International
  • Status ended
  • Start January 1, 2012
  • End September 30, 2015
  • Funding amount € 197,421
  • Project website

Disciplines

Computer Sciences (100%)

Keywords

    Decision Procedures, Non-Boolean, Error Correction, Quantified Formulars, Interpolation

Abstract Final report

In spite of all the effort that goes into verification, the design of integrated circuits has become so complex that critical bugs often make their way into in silicon. Since respins are prohibitively expensive for all but show- stopping bugs, there is often a need for software workarounds for hardware bugs in systems involving both hardware and software components. In QUAINT, we propose to develop automatic methods to construct such workarounds. We will study the repair problem from two sides. On the one hand, we will develop methods to model hardware bugs in such a way that the search for a software workaround is feasible. The tasks include fault localization and solving formulas for a valid repair. Following previous work, we view the repair problem as a game played by two players (the environment and the system) with opposite interests (to violate and to fulfill the specification, resp.). Thus, the repair problem will naturally result in formulas with quantifier alternations. However, modifications are needed to consider available hardware constraints. The second goal is to develop novel methods to evaluate such formulas efficiently and to extract repairs from them. Here, we will use our existing expertise in interpolation for function extraction and quantifier elimination to speed up QBF solving and to generate certificates that allow for efficient repairs. We will also study ways to move beyond the bit level, studying quantified formulas in other logics, in particular using equality logic and uninterpreted functions.

Writing correct software or hardware is very difficult and bugs can have major consequences. For instance, on 9 May 2015, a software problem caused a military Airbus A400M to crash, killing four crew members and injuring two. In order to prevent such disasters, we want to prove software and hardware correct. The classical approach is to first write software and then to prove it, but this seems wasteful. It is preferable to synthesize correct software automatically from a given specification. The synthesis problem is a very difficult one, but in QUAINT we have made significant progress towards making it real. We have focused on two aspects: one is the collaboration between humans and synthesis tools. We have built synthesis tools that automatically construct that part of a program that is particularly difficult for a programmer, but not the parts that are easy. We have also created very efficient synthesis tools by exploring the connection between synthesis and different logics and logic solvers. Our Taiwanese partners, experts in logic, were crucial to these efforts. Finally, the project has contributed to the education of two brilliant young PhD students who have now joined Austrian industry.

Research institution(s)
  • Technische Universität Graz - 100%
International project participants
  • Jie-Hong Jiang, National Taiwan University - Taiwan

Research Output

  • 236 Citations
  • 11 Publications
Publications
  • 2012
    Title Henkin Quantifiers and Boolean Formulae
    DOI 10.1007/978-3-642-31612-8_11
    Type Book Chapter
    Author Balabanov V
    Publisher Springer Nature
    Pages 129-142
  • 2014
    Title How to Handle Assumptions in Synthesis
    DOI 10.4204/eptcs.157.7
    Type Journal Article
    Author Bloem R
    Journal Electronic Proceedings in Theoretical Computer Science
    Pages 34-50
    Link Publication
  • 2014
    Title Suraq — A Controller Synthesis Tool Using Uninterpreted Functions
    DOI 10.1007/978-3-319-13338-6_6
    Type Book Chapter
    Author Hofferek G
    Publisher Springer Nature
    Pages 68-74
  • 2013
    Title Synthesizing multiple boolean functions using interpolation on a single proof
    DOI 10.1109/fmcad.2013.6679394
    Type Conference Proceeding Abstract
    Author Hofferek G
    Pages 77-84
    Link Publication
  • 2012
    Title Automatic Decoder Synthesis: Methods and Case Studies
    DOI 10.1109/tcad.2012.2191288
    Type Journal Article
    Author Liu H
    Journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Pages 1319-1331
  • 2012
    Title Symbolically synthesizing small circuits.
    Type Conference Proceeding Abstract
    Author Ehlers R
    Conference 2012 Formal Methods in Computer-Aided Design (FMCAD)
  • 2012
    Title Unified QBF certification and its applications
    DOI 10.1007/s10703-012-0152-6
    Type Journal Article
    Author Balabanov V
    Journal Formal Methods in System Design
    Pages 45-65
  • 2014
    Title SAT-based methods for circuit synthesis.
    Type Conference Proceeding Abstract
    Author Bloem R
    Conference FMCAD 2014
  • 2014
    Title Synthesis of synchronization using uninterpreted functions.
    Type Conference Proceeding Abstract
    Author Bloem R
    Conference FMCAD 2014
  • 2014
    Title SAT-Based Synthesis Methods for Safety Specs
    DOI 10.1007/978-3-642-54013-4_1
    Type Book Chapter
    Author Bloem R
    Publisher Springer Nature
    Pages 1-20
  • 2013
    Title Synthesizing multiple boolean functions using interpolation on a single proof.
    Type Conference Proceeding Abstract
    Author Bloem R Et Al
    Conference 2013 Formal Methods in Computer-Aided Design (FMCAD)

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