HaRTOP - Hard Real-Time OSI-based Fieldbus Protocol

Research project P 14622 HaRTOP - Hard Real-Time OSI-based Fieldbus Protocol Alexander BAUER 09.10.2000 The aim of the research project "HaRTOP" is the develpopment of a field area network protocol that is based on the widespread OSI conformable fieldbus architecture ANSI/EIA-709.1 (Lon Works) and capable of hard real-time operation. Fieldbusses are used to connect intelligent nodes in distributed control systems. They can replace conventional centralized solutions to save costs e.g. in cabling, system integration and maintenance. The applications of field area networks often require real-time capabilities to ensure that crucial deadlines can be met. Research projects at the Institute of Computer Technology (ICT) have dealt with enhancements of LonWorks for severatl years. A central project in this context is the development of the communication controller LDC which shall solve a lot of problems mainly in high-speed and real-time LonWorks applications. The functionality of this chip must be expanded in the course of this project to provide hard real-time protocol stack implementing the higher protocol layers on a host processor must also be developed. The complete system emerging form this project shall - apart form the hard real-time capability - provide features like clock-synchronization between nodes, automatic membership service, dynamic reconfiguration possibilities, compatibility to conventional solutions and fault tolerance. To allow the independent modification of different layers of a real-time network protocol, everty layer of the protocol stack must provide maximum response time for all its servisex. Therefore each of the seven ANSI/EIA-709.1, different types of simulation will also be required to empirically verify the correctness of the protocol implementation. Apart from the VHDL simulation of the chip, a software model for simulation on a PC as well as an environment simulator must be developed. This test and simulation environment shall then be used to perform extensive functional and temporal verification of the network protocol behavior, which is a crusial necessity for hard real-time systems.

The aim of this research work was the development of a hard real-time, ISO/OSI (Open Systems Interconnect) based, field area network protocol. These protocols are needed for the efficient interconnection of distributed sensors, actuators, controllers, monitoring tools, etc. in automated systems. The wide-spread EIA-709 (LonWorks) standard was taken as a basis for the work and was extended with a hard real-time mode, that guarantees predictable temporal behaviour, a crucial requirement for many field area applications. The `L-Chip`, a flexible high-speed network controller for EIA-709, developed by the Austrian company LOYTEC, represented the state- of-the-art at the start of the project. The most current design was thoroughly analysed towards its hard real-time capabilities. A test bench using a network of L-Chip development boards confirmed the required behaviour predicted by analysis and simulation. For the further development of the hard real-time mode, different strategies and implementation structures for the lower protocol layers were discussed, analysed and evaluated. A flexible event-based model was specified and implemented, integrating both the existing approach using the L-Chip with different communication media as well as new approaches towards a pure software solution. Following was a theoretical analysis of the session and transport protocol layers (layer 4&5) of EIA-709 towards hard real-time behaviour. By restricting some parameters of the corresponding protocol services, a predictable scheduling algorithm could be found that still ensures maximum propagation delays for each transaction. The results of the research work could then be used for the development of the `LISA` SoC (System on Chip), a joint venture of LOYTEC and NEC Electronics. It integrates a CPU core, two control net modules, and various other modules into a single chip. The control net modules contain a hard real-time arbitration mode which is compatible with the L- Chip. Using the RISC CPU core, flexible implementations of the hard real-time protocol as well as various other protocols are possible. The results of the research work have shown that despite contradictory theses, the implementation of an OSI based hard real-time network protocol is feasible. The scalable, open architecture of the protocol stack implementation ensures portability to different hardware and software platforms, which opens up new research and development possibilities for interested parties both in the scientific and the industrial domain.