Clock Synchronization Strategies

The time-triggered technology developed at the Technical University of Vienna over the past twenty years is becoming the technology of choice for the implementation of dependable embedded systems in the automotive, aerospace and process control domains. An essential element of the time triggered technology concerns the establishment of a fault-tolerant global timebase at all nodes of a distributed application. Fault-tolerant Glock synchronization within a single cluster has been extensively investigated at the TU Vienna and elsewhere. In this basic research project the issues related to multi-cluster fault-tolerant Glock synchronization in a distributed time- triggered architecture for safety critical real-time applications will be investigated. Multi-cluster architectures impose additional requirements an the Glock synchronization process, because not all local clocks are in the Same cluster anymore. We will investigate the impacts of various multi-cluster architectures an the quality and stability of internal Glock synchronization by means of simulation and by an expeimental setup and measurement of the most promising alternatives. A simulation model will be created that allows to build up different multi-cluster configurations and that will cover all aspects of the TTP protocol related to Glock synchronization. The project consists of two phases: during the first phase promising architectures shall be identified by means of simulation. The aims of the second phase are realization and evaluation of these architectures in hardware configurations.

Distributed fault-tolerant real-time systems are increasingly deployed for safety-critical applications in automotive, aeronautic and process control domains. Time-triggered systems are becoming the technology of choice due to their deterministic behaviour. Many such systems today consist of a single cluster, i.e. a set of spatially separated computer nodes, each running a local clock, that execute a distributed application in a cooperative manner communicating over a dedicated communication medium. A key issue in time-triggered systems is the establishment of a fault-tolerant global time base among all nodes in a cluster by means of periodic synchronization of the node-local clocks. It is reasonable to build up large real-time systems from several clusters into so-called multi-cluster systems. It was the aim of this basic research project to identify measures and means that improve the quality of synchronization in time-triggered multi-cluster systems. The main contribution of this project is the design of a novel clock synchronization algorithm that combines clock state synchronization and clock rate synchronization. The idea is to bring the clock rates of all nodes in a cluster into agreement with the clock rate of a so-called rate master node. The quality of synchronization depends, among other factors, on the quality of the clocks involved in the synchronization process. The new algorithm improves the quality of clock synchronization while reducing the need for expensive high-quality oscillators. This is especially meaningful in a market of mass production (like the emerging automotive market for drive-by-wire systems) where the cost of every single component is scrutinized in order to find alternatives that are less costly. Therefore, the new algorithm provides dependability at affordable cost. Further, the new algorithm is composable with regard to clock synchronization. If a cluster is externally synchronized (e.g. connected to a GPS receiver), only the rate master node has to be modified; the other nodes in the cluster remain unchanged. Finally, the algorithm is suited to solve the synchronization problem in multi-cluster systems and provides a remarkably better quality of synchronization compared to existing approaches. The simulation environment SIDERA was written from scratch. SIDERA provides simulation of various real-time protocol services like system start-up, communication, clock synchronization, membership service and protocol error detection and handling. SIDERA was used for the design and evaluation of the new algorithm. The algorithm was validated using different hardware configurations, namely TTP/C and Time-Triggered Ethernet.