Vertical, strained 1D silicon Nanostructures and Devices

Elucidating `Vertical strained 1D silicon Nanostructures and Devices` is a complex task, which requires an interdisciplinary consortium capable of addressing all relevant issues from metal nanoparticle template formation, 1D silicon nanostructure growth, analysis of mechanical and electrical properties and device formation. In this proposal we suggest therefore a transnational cooperation between the Max-Planck-Institute of Microstructure Physics (MPI), Halle (D), the Institute for Solid State Physics (IFK), Jena (D), the Materials Measurement Research Group (EMPA), Thun (CH), the Nanostructure Research Group (EPFL) in Lausanne (CH) and the Institute for Solid State Electronics (FKE), Wien (A). Initially, we will synthesize 1D silicon nanostructures at specific sites with well-defined lengths and diameters using the metal catalysed so called vapor-liquid-solid growth process. The positioning of the metal (Ga, Au, Al) nanoparticles will be carried out using ion beam techniques. In situ SEM observation in combination with in-situ electrical testing and nano-manipulation devices will be used to explore the growth mechanisms and the electronic and mechanical properties of the 1D nanostructures. In a second step we will integrate the 1D nanostructures in devices such as pn-junctions and vertical field-effect- transistors (FETs). For this purpose several aspects of contact formation as well as abrupt pn-junction formation and the deposition of dielectrics have to be solved. Different, partly self-aligned processes of contact formation via wafer bonding will be exploited. From realized assemblies of multiple 1D nanostructures in vertical functional test structures such as pn-junctions and field-effect transistors, we will extract their fundamental electrical properties. With the ability to apply strain to individual 1D silicon nanostructures and their assemblies, we will investigate the effect of strain on the electrical properties. The consortium will provide for the required competences: MPI/ IFK: growth of 1D silicon nanostructures, wafer bonding, structural characterization, FKE: nano-template synthesis, 1D nanodevice processing and characterization, EMPA/EPFL: in-situ SEM studies for 1D silicon nanostructure formation, electronic and mechanical properties characterization, in-situ straining of 1D nanostructures by nanomanipulators in the SEM.

Nanowire devices have received considerable attention as regards used in integrated nanoscale electronics as well as for studying fundamental properties in small dimensions. In particular, Si-nanowires integrated in devices, have been identified as promising candidates for post-CMOS logic elements owing to their potential compatibility with existing semiconductor technology. Within this project we explored a scalable approach for the parallel integration of vertical and self contacting Si- nanowires. By combining well known top down semiconductor processing techniques and epitaxial Si-nanowire growth with control of the nanowire location and orientation we circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach. In developing a vertical gate all around Si-nanowire MOSFET it was important to control the geometrical and above all the electrical properties of the nanowires, which strongly depend on the diameter as well as the crystallographic orientation and defect structure of the nanowires. Our approach was therefore directed to produce single crystal Si- nanowires with uniform diameters and controlled growth directions. The particular synthesis technique we focused on was the most rational and tunable vapor-liquid-solid (VLS) growth mechanism, superior for the fabrication of nm-sized wires. In the VLS growth of Si-nanowires, gold (Au) nanoparticles were used as catalyst and SiH4 as precursor gas. While the geometry of the nanowires did not impose strong demands on the fabrication process, proper surface preparation before catalytic Au seed deposition appeared to be crucial for well controlled nanowire growth. We made obvious, that a thin native oxide layer on the Si substrate - as is present under most technological conditions - or a thin layer of oxide formed on top of the catalytic Au particle, restrain nucleation and nanowire growth. Further we demonstrated that the growth direction of epitaxially grown Si nanowires changes with the total pressure in the growth chamber. To the best of our knowledge the influence of the pressure on the growth rate and the morphology was to some extent investigated but up to now a pressure dependency of the growth direction has not been discussed elsewhere. By dynamically changing the system pressure during the growth process, kinked Si- nanowires were synthesized in a well reproducible manner. By controlling size, density, location and growth direction of nanowires, our method enabled the controlled incorporation of nanowires into the proposed vertical gate all around MOSFET device. This technique in combination with other nanofabrication methods, due to its scalability and ease of device fabrication, goes beyond the current state-of-the-art assembly of nanowire based devices such as transistors and sensors and may be used as a platform for building more complex architectures such as hierarchical 3D modules.