ALD of nanoscale films on silicon nanowires

In its continuous struggle with the all-time present doctrine of Moore`s law semiconductor research and development scales its devices to ever-smaller dimensions. The critical dimensions of a single MOS transistor are now in the range of a few tens of nanometers. The golden era of the poly-silicon/silicon-dioxide/silicon system, which successfully enabled CMOS-device scaling for decades, seems to reach its end within the next two or three technology generations due to tunneling leakage runaway. As devices get smaller and smaller, critical film thicknesses have to be more and more reduced, approaching now monolayer dimensions. Thus, the physico- chemical properties of the surface and the interfaces in these structures gain more and more importance, and hence dramatically influence the electrical characteristics of the resulting devices. To face the grand challenges associated with future device scaling, planar bulk CMOS has to incorporate new gate stack processes and materials. Therefore, semiconductor research and development institutions incessantly search for new thin film materials able to substitute the silicon-dioxide gate-isolator, as well as the poly-silicon gate. Beyond any material choice, the deposition technology in the few-nanometer range plays a decisive role for further process integration. Hereby, Atomic Layer Deposition (ALD) has emerged as the most suitable approach. Moreover, as bulk devices approach more and more to fin-like body structures, quasi 1-D nanostructures in the shape of nanowires are proposed for application in future silicon technology. By applying both, ALD for the gate stack, and Si-nanowires for the device body, a device scaleable to a few nanometers appears to be possible. A unique versatility in terms of geometrical dimensions and architecture might provide the key properties which could extend the technology to and probably beyond the actual end of the roadmap. The main objective of this project is to explore atomic layer deposition of nanoscale films on as-grown silicon nanowires and to characterize their properties in view of a latter application as electronic devices. By investigating the material and electrical properties in dependence of the processing parameters, a basic understanding of ultra- thin dielectrics on as-grown silicon nanowires as well as of metals for electrical contacting of these structures shall be gained. For these purposes, an assembly of test modules should be generated, enabling the exploration of the morphological, physico-chemical and electrical properties. Ultra-thin, that is a few nm thick dielectric layers (Al 2 O3 , HfO 2 , ZrO2 , and rare-earth metal oxides) will be deposited by ALD on as-grown silicon nanowires. On top of these layers, different metallic electrodes (TiN, W and Pt) will be deposited to form device-like structures that can furthermore be electrically investigated. The material systems will be investigated in view to their thermodynamic stability during different thermal processing steps. Qualitative and quantitative classifications by physico-chemical and electrical characterization techniques will sustain data extraction. Thereby, national and international cooperation, addressing both, processing and characterization, will support project progress and intense networking. By means of a detailed research plan, a series of material combinations will be successively processed and evaluated to achieve three main goals: (i) a comprehensive study on the key properties of ALD-nanoscale- film/silicon nanowire interfaces, (ii) an adaptation of the electrical characterization techniques to the nanoscale- regime, and (iii) benchmarking of compatible material combinations for the use in future nanodevices.

In its continuous struggle with the all-time present doctrine of Moore`s law semiconductor research and development scales its devices to ever-smaller dimensions. The critical dimensions of a single MOS transistor are now in the range of a few tens of nanometers. The golden era of the poly-silicon/silicon-dioxide/silicon system, which successfully enabled CMOS-device scaling for decades, seems to reach its end within the next two or three technology generations due to tunneling leakage runaway. As devices get smaller and smaller, critical film thicknesses have to be more and more reduced, approaching now monolayer dimensions. Thus, the physico- chemical properties of the surface and the interfaces in these structures gain more and more importance, and hence dramatically influence the electrical characteristics of the resulting devices. To face the grand challenges associated with future device scaling, planar bulk CMOS has to incorporate new gate stack processes and materials. Therefore, semiconductor research and development institutions incessantly search for new thin film materials able to substitute the silicon-dioxide gate-isolator, as well as the poly-silicon gate. Beyond any material choice, the deposition technology in the few-nanometer range plays a decisive role for further process integration. Hereby, Atomic Layer Deposition (ALD) has emerged as the most suitable approach. Moreover, as bulk devices approach more and more to fin-like body structures, quasi 1-D nanostructures in the shape of nanowires are proposed for application in future silicon technology. By applying both, ALD for the gate stack, and Si-nanowires for the device body, a device scaleable to a few nanometers appears to be possible. A unique versatility in terms of geometrical dimensions and architecture might provide the key properties which could extend the technology to and probably beyond the actual end of the roadmap. The main objective of this project is to explore atomic layer deposition of nanoscale films on as-grown silicon nanowires and to characterize their properties in view of a latter application as electronic devices. By investigating the material and electrical properties in dependence of the processing parameters, a basic understanding of ultra- thin dielectrics on as-grown silicon nanowires as well as of metals for electrical contacting of these structures shall be gained. For these purposes, an assembly of test modules should be generated, enabling the exploration of the morphological, physico-chemical and electrical properties. Ultra-thin, that is a few nm thick dielectric layers (Al 2 O3 , HfO 2 , ZrO2 , and rare-earth metal oxides) will be deposited by ALD on as-grown silicon nanowires. On top of these layers, different metallic electrodes (TiN, W and Pt) will be deposited to form device-like structures that can furthermore be electrically investigated. The material systems will be investigated in view to their thermodynamic stability during different thermal processing steps. Qualitative and quantitative classifications by physico-chemical and electrical characterization techniques will sustain data extraction. Thereby, national and international cooperation, addressing both, processing and characterization, will support project progress and intense networking. By means of a detailed research plan, a series of material combinations will be successively processed and evaluated to achieve three main goals: (i) a comprehensive study on the key properties of ALD-nanoscale- film/silicon nanowire interfaces, (ii) an adaptation of the electrical characterization techniques to the nanoscale- regime, and (iii) benchmarking of compatible material combinations for the use in future nanodevices.