Comprehensive Physical Modeling of Hot-Carrier Induced Degradation

Although degradation induced by hot-carriers was first reported in the 1970s, a remedy against it is still missing. As a result, transistors of practically every technology node suffer from hot-carrier degradation (HCD). Device aging under hot-carrier stress occurs both in the case of scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) employed in logic applications as well as in the case of high-voltage transistors, used e.g. in automotive applications. HCD drastically affects the device life-time and a reliable model capable of accurate predictions is of great importance. Such a model would be expected to allow for a comprehensive description of the degradation impact on device performance and provide recommendations for device development engineers on how to improve transistor immunity to HCD. As a general result, investigations of hot-carrier degradation should drastically improve the quality of commercial devices. Notwithstanding the fact that a substantial number of HCD modeling approaches exists, these approaches often do not capture the physics behind hot-carrier degradation and rely on some empirical considerations. In general, the physical picture of this degradation mode is still not fully understood and thus cannot yet serve as a basis for a comprehensive model. Moreover, due to the overall complexity, modeling of HCD not only requires a correct description of the defect build-up kinetics during stress. The information on the driving force of defect generation and on the damage impact on the device performance are also of great importance. As a result, the existing physics- based models of HCD have a rather limited applicability because they do not consolidate all these aspects within a same framework. The main goal of this project is to develop a comprehensive physics-based framework for hot-carrier degradation modeling. We conditionally separate the matter into three main aspects. First, the microscopic mechanisms for defect generation will be investigated and modeled. Second, since the degradation is triggered by energy deposited by carriers, the model has to essentially include an accurate carrier transport module providing information on how hot carriers are. Finally, the effect of the produced damage on the device characteristics has to be properly modeled. Our model will integrate all these aspects within a single framework, thereby completing the chain between the microscopic and device simulation levels. Investigations will be carried out on a wide range of state- of-the-art devices fabricated on various technologies, including ultra-scaled modern MOSFETs, long-channel transistors and high-voltage devices with a complicated architecture. The results obtained within the project will be disseminated to the scientific community and the model will be implemented into and made available through the software release channels of our Institute.

The International technology roadmap for semiconductors considers the problem of transistor reliability as a major issue to be addressed in order to ensure further evolution of modern micro/nanoelectronics. Among the different degradation modes, hot-carrier degradation (HCD) is suggested to be the major concern. This is because in modern metal-oxide-semiconductor field-effect-transistors (MOSFETs) the operating voltage cannot be scaled beyond certain values as the linear dimensions continue to shrink, thereby resulting to high electric fields in the device and thus significant HCD. Therefore, a detailed understanding of the degradation physics is required followed by an accurate physics-based description. Within this project, we developed and validated the first physics-based model for HCD which covers and links three main aspects related to this effect: thorough carrier transport treatment, a microscopic description of the defect generation mechanisms, and modeling of the degraded devices. This model assumes that HCD is related to the dissociation of silicon-hydrogen bonds at the interface driven by single- and multiple-carrier bond-breakage mechanisms. The rates of these mechanisms (as well as the rates of their superpositioned effect) are modeled using the carrier energy distribution function (DF) which is obtained by solving the Boltzmann transport equation (BTE) for a particular device architecture and defined stress/operating conditions. To accomplish this task we use the deterministic BTE solver ViennaSHE, which has been also developed at our Institute. ViennaSHE considers the full band structure of silicon as well as scattering mechanisms such as impact ionization, scattering at ionized impurities, electron-phonon and electron-electron interactions. In particular electron-electron scattering (EES) determines HCD in short-channel devices (<100nm) and is therefore an important component of the model. The model has been validated against an extensive set of HCD experimental data acquired in scaled transistors as well as in high-voltage devices over a wide range of stress conditions. For all these devices we carefully checked the importance of each model ingredient and obtained a number of non-trivial conclusions. First, in contrast to the previous understanding, the multiple-carrier process of Si-H dissociation can play a substantial role even in high-voltage devices, while the single-carrier mechanism can be dominant in ultra-scaled MOSFETs. Second, at high stress voltages EES can make a significant contribution to HCD also in long-channel transistors. Finally, even in devices with gate length of less than 100nm HCD can become less pronounced at higher temperatures and the temperature behavior of this phenomenon is determined by the combination of stress conditions and device architecture. Typically, if one switches from accelerated stress to milder operating conditions, the degradation physics change, thereby making simplified empirical models not applicable. Careful validation of our approach and detailed understanding of the physical picture behind HCD make our model predictive, i.e. the model allows for device life-time extraction under both stress and operating conditions.