Hybrid Heterostructure Nanowires

Semiconductor nanowires are a promising geometry for next-generation electronic devices, exploiting the reduced density of states and quantization effects and allowing higher transit frequencies at reduced leakage currents. Additionally, the large surface to volume ratio makes them an ideal candidate for chemical sensing applications or for photovoltaic energy conversion. All these applications benefit from the wide selection of materials, which can be integrated onto the e.g. Si/Ge platform by using epitaxially grown nanowires. Their functionality can be extended further through semiconductor heterostructures, which allow to design the electronic structure for specific applications. The main goal of this project is the fabrication, characterization and optimization of hybrid nanowire heterostructures, consisting of Si/Ge and III-V materials. The small contact area between substrate and nanowire or between two nanowires provides the ability to join materials with different lattice-constant and chemical bonding together and characterize these heterojunctions in an unstrained and defect-free case. In particular, we will investigate the growth of III-V nanowires on Si/Ge nanowires and vice versa. Until now most research work was concentrating on Si/Ge or III-V nanowire heterostructures, therefore the approach to integrate both material groups is a logical consequence. The novelty of such structures requires efforts to establish the epitaxial growth and characterize these hybrid nanowires structurally, optically and electronically. Possible approaches, which are point of investigation in this project, are axial Si/Ge/III-V heterostructures, III-V branches on Si/Ge nanowires and the growth of Si/Ge structures on III-V nanowires. Finally, the combination of all these techniques will allow the fabrication of Si/Ge/III-V nanowire heterostructures with multiple interfaces and III-V quantum dots, embedded into group IV nanowires. For this purpose, we will also investigate novel catalysts for improved heterostructure growth and electrical contacts. The electronic properties of these heterostructures will be investigated by optical experiments and electronic transport studies on single nanowires and small ensembles. This project will therefore provide a way to integrate the flexibility and functionality of III-V heterostructures with Si/Ge established device technology. As these are novel structures, a further goal is the development of prototype devices, which are based on nanowire heterostructures, but allow the integration with planar device geometries. We propose different device geometries, which will allow the integration of epitaxially grown III-V or hybrid nanowires with conventional Si/Ge device fabrication techniques. These devices will be based on silicon-on-insulator substrates, where nanowires will be grown in place without the need for harvesting, positioning and contacting dispersed wires. These will allow to make the transition from growth and material characterization towards functional electronic or optoelectronic devices, which then can be developed further, focusing specific applications.

Nanowires allow the integration of different materials with established silicon-based electronic platforms. This is mainly enabled by the small contact area between nanowire and substrate, which allows efficient relaxation of strain and therefore a defect-free growth. We exploited this principle to address key steps that are of interest for hybrid systems of CMOS electronics with III-V semniconductor-based optoelectronic components. The synthesis of nanowires at well-defined positions in an ultra-high vacuum compatible process a key requirement for device integration was achieved through focused ion beam implantation of Ga arrays into the substrate, which were then used as a catalyst droplets. Compared to other lithography-based techniques, the distinct feature of this process is the complete absence of organic chemicals, which could provide a risk of cross-contamination for epitaxial growth facilities. We furthermore studied the incorporation behavior of boron into GaAs layers and nanowires to enable strain-engineering in future devices. In contrast to other group III elements, B was found to incorporate both at cation and anion sites and therefore leads to p-type conductivity in nominally undoped structures. The unintentional doping could be reduced through optimized growth parameters. In the case of nanowires, we found B-segregation to the surface, which requires further studies but also opens new possibilities for sensing applications. Core-shell nanowires were fabricated to enable future application in optoelectronic devices. GaAs nanowires were used as a basis for radial heterostructures with InGaAs quantum wells for emission wavelengths between 900 1000 nm. Multi-shell structures with identical or varying quantum well widths allow to gain insight in to the carrier distribution within the nanowire, which is strongly influenced by the proximity of surface states. Samples with different quantum well thicknesses always lead to photoluminescence from the outermost rather than the widest quantum well. Understanding these band-bending effects will be a key requirement to pave the way for more complex device prototypes. This project therefore did address three important aspects of III-V nanowires positioning to enable well defined device geometries, the growth of novel materials that are difficult to fabricate in bulk or layer growth and groundbreaking work for the integration of III-V semiconductors with Si for hybrid optoelectronic structures or integrated sensors.