Single-Trap Characterization Methodology for Nanoscale MOSFETs

The aggressive scaling of the metal-oxide-semiconductor field-effect transistor has resulted in nanoscale devices containing just a handful of defects. These randomly distributed defects lead to a time-dependent variability in the transistor characteristics. While this effect is highly detrimental for normal device operation, it provides a unique opportunity to study the physical properties of single individual defects. Using a sophisticated methodology we can experimentally investigate the whole life cycle of single defects starting from their creation, followed by charging/discharging and terminated by annihilation. Defects can be conditionally separated into interface and oxide traps. For both types of defects the average time constants for the transition between the various states vary by many orders of magnitude. While a lot of progress has been made recently in understanding the defect dynamics of easily recoverable defects, not that much is known about the more permanent defects. Most interestingly, most of them can be annealed at higher temperatures. The main goal of this project is to improve our understanding of those more permanent defects, as they are expected to dominate the lifetime distribution. In particular, these defects are most probably the origin of the `permanent` component of the damage produced by hot-carrier and long-term bias temperature stresses. Furthermore, we will explore the wide distribution of the defect properties in a range of state-of-the-art transistors fabricated on different technologies (SiO 2 , SiON, and high-k gate stacks). To investigate these defects we plan to extend the time dependent defect spectroscopy by applying special stress and recovery temperature ramps combined with controlled bias pulses. Such recovery ramps are used to shift the time constants towards lower values, thereby making ultra-slow defects visible in the experimental time window. For this purpose we will use local on-chip polyheater systems surrounding the devices under test which offer rapid heating/cooling dynamics. In order to identify the distribution of the defect properties, measurements will be performed in parallel on packaged devices with integrated polyheaters. The statistical information obtained from our experiments will considerably enhance our understanding of the physical mechanisms behind defect creation and annealing. Furthermore, it will enable the prediction of device lifetimes with unprecedented accuracy, while the experimental methodology is expected to have a considerable impact on the scientific state-of-the-art.

The international technology roadmap for semiconductors (ITRS) lists bias temperature instability (BTI) and hot-carrier degradation (HCD) as the most difficult challenges which must be properly understood and modeled. Although extensive experimental and theoretical studies on these phenomena have been performed, there are still open issues in understanding the nature and behavior of defects contributing to BTI and HCD. Even more dramatic, in circuits transistors are rarely subjected to idealized BTI (high gate bias and no drain bias) or HCD (low gate bias and high drain bias) conditions. Nevertheless, only a limited number of studies is available on mixed BTI/HCD stress. For a more realistic life time prediction it is necessary to extend existing models towards mixed BTI/HCD conditions. Within this project, we focused on the impact of mixed mode stress conditions on single oxide defects as well as on a large ensemble of traps in order to characterize the device degradation, such as the shift of the threshold voltage, in a more general way. Both individual degradation phenomena are reasonably well understood and rather intricate models have been developed which are able to capture the characteristics of each mode. However, only a handful of publications are devoted to the interplay of both mechanisms, and in particular, the implications of an applied drain bias onto oxide defects. Our experimental studies showed that with increased drain bias, the recoverable component, typically attributed to defects within the gate oxide, decreases, while at the same time the overall degradation increases. Commonly accepted assumptions imply that source-sided defects would be rather unaffected by an applied drain stress. Quite contrary to this, we have shown in this project that even defects located in the vicinity of the source can be heavily affected by a drain bias. Within this project, we presented a first systematic experimental data set and developed a theoretical framework to accurately describe this complex and rather puzzling behavior. To validate our modeling approach, we compared the simulation results and experimentally recorded characteristics for single-oxide defects for various stress combinations. Furthermore, we applied the framework to a large ensemble of oxide traps to understand the reduction in the contribution of oxide defects with increased mixed-mode stress in MOSFET devices.