SPAD-based fiber optical CMOS receivers

Because of thermal noise, common analogous optical CMOS receivers need a rather high optical input power - corresponding often to more than 10,000 photons per bit. Photon statistics however sets the physical limit of only a few ten photons (in average). The electrical power consumption of analogous receivers is high and they occupy a large chip area. In pure electronic integrated circuits (ICs), however, many analogous circuit blocks were already replaced by digital signal-processing. This project will for the first time show that Single-Photon Avalanche Diodes (SPADs) allow due to their very high amplification to realize digital optical receivers as optoelectronic integrated ICs, which come close to the quantum limit. These SPAD optical receivers will be verified in data transmission experiments via plastic and silica optical fibers. However not each photon is detected by these SPADs what would be expected from their name. The P+/N- well SPADs integrated in CMOS so far possess a thin absorption/multiplication zone limiting the photon detection probability (PDP) often to less than 25% (especially for red and near-infrared light), which means that in average 4 photons are needed, that one of them causes a huge avalanche to trigger a digital circuit. Here the project comes in by investigating innovative SPADs for data rates up to 1Gbit/s, whose PDP shall reach 90% by exploiting a thick absorption zone and separate multiplication zone, which are integrated for the first time together with circuits in high-voltage CMOS. These innovative SPADs furthermore possess a considerably smaller capacitance and will therefore reduce the avalanche charge and afterpulsing bringing low bit error ratios into reach. To obtain usable digital optical receivers, the SPADs dark count rate, afterpulsing and optical crosstalk have to be investigated and reception errors have to be minimized. The necessary number of SPADs and the achievable bit-error-ratio in dependence on optical input power will be investigated. In addition improved trigger circuits with considerably reduced threshold and fast quenching circuits are investigated again to minimise avalanche charge and afterpulsing. Furthermore high-frequency gating circuits are tested to aim towards data rates of up to 1Gbit/s. A complete model for SPADs and their bit-error-ratio will be derived. Test detectors and receiver circuits will be fabricated as Application Specific Integrated Circuits (ASICs) to verify the innovative approaches towards digital SPAD optical receivers. Cheap high data rate LEDs possess a high extinction ratio and enable to reduce the optical input power compared to analogous optical receivers by possibly more than a factor of 100. Summarising, innovative SPADs and new small-area current-saving digital receivers are investigated to verify a new generation of robust optical receivers and sensors with considerably improved sensitivity experimentally.

Because of thermal noise, common analogous optical CMOS receivers need a rather high optical input power - corresponding often to more than 10,000 photons per bit. Photon statistics however sets the physical limit of only a few ten photons (in average). The electrical power consumption and chip area of analog receivers are large. In pure electronic integrated circuits (ICs), however, many analogous circuits were already replaced by digital signal-processing. This project showed that Single-Photon Avalanche Diodes (SPADs) allow due to their very high amplification to realize a kind of digital optical receiver ICs, which approach to the quantum limit by eliminating electronic noise. These SPAD receivers were verified in data transmission experiments via silica optical fibers. However not each photon is detected by known SPADs - what would be expected from their name. The P+/N-well SPADs integrated in CMOS so far possess a thin absorption zone limiting the photon detection probability (PDP) to less than 25% for red and near-infrared light, which means that in average 4 photons are needed, that one of them causes an avalanche to trigger a digital circuit. Here the project came in by investigating innovative SPADs (integrated for the first time together with circuits in high-voltage CMOS) with a PDP of up to 90% by exploiting a thick absorption and separate multiplication zone. These innovative SPADs furthermore possess a considerably smaller capacitance and reduce avalanche charge and afterpulsing bringing low bit error ratios for usable SPAD receivers into reach. For enough SPADs, these parasitic effects do not occur in all SPADs within the same bit. A light signal, however, must cause a detection in each SPAD. The necessary number of SPADs and the achievable bit-error-ratio was investigated. In addition improved trigger circuits with considerably reduced threshold and fast quenching circuits were investigated - again to minimise avalanche charge and afterpulsing. SPAD receivers were tested up to 200Mbit/s. A model for SPADs inclusive PDP and their bit-error-ratio was derived. Test detectors and receiver circuits were fabricated as Application Specific Integrated Circuits (ASICs) to verify the innovative approaches towards digital SPAD optical receivers. The sensitivity gap of linear-mode avalanche diode receivers of about 20dB to the quantum limit was reduced to 8dB with SPAD receivers in this project. Summarising, innovative SPADs and new small-area current-saving digital receivers were investigated to verify a new generation of robust optical receivers and sensors with considerably improved sensitivity experimentally.