3D Solution of the Boltzmann Equation on Supercomputers
3D Solution of the Boltzmann Equation on Supercomputers
Disciplines
Electrical Engineering, Electronics, Information Engineering (20%); Computer Sciences (30%); Mathematics (30%); Physics, Astronomy (20%)
Keywords
-
Spherical Harmonics,
Boltzmann Equation,
Semiconductors,
Simulation,
Supercomputing
To further enhance the energy efficiency of desktop computers, laptops, and smartphones, the nano-scale building blocks of microchips, so-called transistors, need to be designed such that they use less space, draw less power, and operate faster. Such improvements become increasingly difficult and require sophisticated fabrication technologies. One of the most recent developments is to replace conventional quasi-two-dimensional transistor layouts with more complicated, fully three-dimensional transistor geometries. Unfortunately, such three-dimensional geometries are much harder to handle for computer-aided design tools, because significantly higher computational power is required. Scientists and engineers thus face a situation very familiar to a broad range of computer gamers: Their workstation computer is fast enough for detailed two-dimensional simulations (or games graphics), but too slow for three-dimensional simulations (or game graphics) at high details the latter take too long to complete (or game graphics is stuttering) to be practical. To enable highly detailed three-dimensional device simulations, parallel algorithms for the solution of the Boltzmann equation will be developed in this project so that the computational power of supercomputers such as the Vienna Scientific Cluster can be leveraged for the design of future transistor generations. An efficient distribution of the computational workload over a supercomputer is, however, very challenging: Each processor can only work on a small subsection of the transistor, but at the same time all processors need to exchange information about their local computations such that the individual computations from each processor result can be composed to a correct overall simulation. By the end of this project we expect that our simulations will result in higher accuracy and detail than any other simulations of fully three-dimensional transistors has achieved before. The developed algorithms will also be of interest to computational scientists in related areas, for example airplane designers seeking to minimize fuel consumption by simulating airfoils.
The funded research has led to better simulation tools that can make modern electronic equipment such as computers, laptop, and smartphones faster, smaller, and less power-hungry. To achieve this, the research team has developed a simulator that can leverage the power of supercomputers with thousands of processors. They can now simulate the small building blocks (transistors) of electronic devices at an unprecedented level of detail. An efficient distribution of the computational workload over a supercomputer poses the following challenge: Each processor can only work on a small subsection of the simulation. So, while the local solution to the part of the problem assigned to a single processor may be correct from the respective processor's point of view, carefully piecing together the individual partial solutions is tricky. Hence, processors need to exchange information about their local computations to form a global solution. This is in analogy to building a house: Individual workers can independently set up different sections of the walls; and yet, the work needs to be sufficiently coordinated such that walls match precisely at the interfaces. The researchers have successfully developed and implemented the algorithms necessary for running simulations on supercomputers. They employ hierarchical methods, in which processors exchange information as fast as possible with as little redundancy as possible. To keep the analogy of building a house: Workers do not need to communicate with every other worker all the time, but only a few times to selected communication partners. The benefit of these new tools are manifold. Not only is it possible to calculate whether and how much current flows through a device, but also to zoom into details of the current flow. One can investigate the exact distribution of which charge carriers (electrons) flow fast and which flow rather slowly. Since the fastest-flowing carriers may damage and my ultimately result in failure of the device, the results can for example be used to improve the reliability of electronic components. This is especially of interest for the automotive sector, where component failure in an electric vehicle may - in the worst case - result in fatal accidents. The results of this research are available to the general public as free open source software. On the one hand, the researchers had to develop general purpose functionality that can also be used for other simulations by researchers and industrial users worldwide. These features have also been contributed to the popular solver package PETSc for reuse by other groups. On the other hand, the full semiconductor device simulation is available in the ViennaSHE simulator. The code is hosted on the popular code platforms GitHub and SourceForge.
- Technische Universität Wien - 100%
Research Output
- 706 Citations
- 20 Publications
- 1 Policies
- 1 Software
- 4 Disseminations
-
2018
Title High Performance Computing Type Book Author Sosonkina Publisher The Society for Modeling and Simulation International Link Publication -
2018
Title Lösung der Poisson Gleichung auf Supercomputern Type Other Author Selinger -
2018
Title Achieving Portable Performance Across Architectures with PETSc Type Conference Proceeding Abstract Author Mills Conference SIAM Conference on Parallel Processing for Scientific Computing Link Publication -
2017
Title Semiconductor Device Simulation Approaches for Massively Parallel Computing Architectures Type Conference Proceeding Abstract Author Rupp Conference SIAM Conference on Computational Science and Engineering Link Publication -
2018
Title Characterization and Physical Modeling of the Temporal Evolution of Near-Interfacial States Resulting from NBTI/PBTI Stress in nMOS/pMOS Transistors DOI 10.1109/irps.2018.8353540 Type Conference Proceeding Abstract Author Grasser T -
2020
Title Toward Performance-Portable PETSc for GPU-based Exascale Systems DOI 10.48550/arxiv.2011.00715 Type Preprint Author Mills R -
2020
Title Preparing sparse solvers for exascale computing DOI 10.1098/rsta.2019.0053 Type Journal Article Author Anzt H Journal Philosophical Transactions of the Royal Society A Pages 20190053 Link Publication -
2020
Title Insulators for 2D nanoelectronics: the gap to bridge DOI 10.1038/s41467-020-16640-8 Type Journal Article Author Illarionov Y Journal Nature Communications Pages 3385 Link Publication -
2021
Title Crystalline insulators for scalable 2D nanoelectronics DOI 10.1016/j.sse.2021.108043 Type Journal Article Author Illarionov Y Journal Solid-State Electronics Pages 108043 -
2019
Title A Flexible Shared-Memory Parallel Mesh Adaptation Framework DOI 10.1109/iccsa.2019.00016 Type Conference Proceeding Abstract Author Gnam L Pages 158-165 -
2021
Title The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials DOI 10.1038/s41928-020-00529-x Type Journal Article Author Knobloch T Journal Nature Electronics Pages 98-108 Link Publication -
2020
Title On the suitability of hBN as an insulator for 2D material-based ultrascaled CMOS devices DOI 10.48550/arxiv.2008.04144 Type Preprint Author Knobloch T -
2019
Title Balancing Run-Time Customization and Compile-Time Optimization in HPC Type Conference Proceeding Abstract Author Rupp Conference European Numerical Mathematics and Advanced Applications Conference 2019 Link Publication -
2019
Title Posedness of Stationary Wigner Equation Type Conference Proceeding Abstract Author Nedjalkov Conference International Wigner Workshop Pages 32-33 Link Publication -
2019
Title A Gauge-Invariant Wigner Equation for General Electromagnetic Fields Type Conference Proceeding Abstract Author Nedjalkov Conference International Workshop on Computational Nanotechnology Pages 67-68 Link Publication -
2020
Title The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release DOI 10.1109/irps45951.2020.9129198 Type Conference Proceeding Abstract Author Grasser T Pages 1-6 -
2021
Title Toward performance-portable PETSc for GPU-based exascale systems DOI 10.1016/j.parco.2021.102831 Type Journal Article Author Mills R Journal Parallel Computing Pages 102831 Link Publication -
2020
Title Insulators for 2D nanoelectronics: the gap to bridge DOI 10.18154/rwth-2020-07464 Type Other Author Illarionov Y Link Publication -
2020
Title Vendor-Optimized vs. Portable Performance: Approaches to Get Both Type Conference Proceeding Abstract Author Rupp Conference SIAM Conference on Parallel Processing for Scientific Computing Link Publication -
2021
Title Parallel Solver Study for Solving the Boltzmann Transport Equation using Spherical Harmonics Expansions on Supercomputers Type Conference Proceeding Abstract Author Ribeiro Conference International Workshop on Computational Nanotechnology Pages 97 - 98 Link Publication
-
2022
Link
Title ViennaSHE 1.3.0 DOI 10.5281/zenodo.6517526 Link Link
-
2018
Link
Title PETSc Tutorial at TU Delft, 2019 Type Participation in an activity, workshop or similar Link Link -
2019
Link
Title PETSc User Meeting 2019 Type Participation in an activity, workshop or similar Link Link -
2017
Link
Title PETSc User Meeting 2017 Type Participation in an activity, workshop or similar Link Link -
2018
Link
Title PETSc User Meeting 2018 Type Participation in an activity, workshop or similar Link Link