Ultimate Scaling and Performance Potential of MoS2 FETs

2D materials beyond graphene have gained enormous attention since a transistor with a two- dimensional (2D) molybdenum disulfide (MoS2) channel was demonstrated in 2011. Currently, research on these materials for electronic applications is underway worldwide, in particular on the 2D transition metal dichalcogenides (TMD), with MoS2 as the most prominent representative. MoS2 possesses a sizeable bandgap and therefore shows great promise for future digital electronics. The processing technology for MoS2, however, is still in its infancy and many questions regarding the potential of MoS2 transistors are still open. This makes it currently extremely difficult, if not impossible, to assess the performance and scaling limits of MoS2 transistors and to judge the prospects of these devices for future electronics. This situation provides the motivation for the present project, which is focused on the fabrication technology, theory and simulation of ultimately scaled MoS2 field effect transistors (FETs). The three project partners, two from Germany and one from Austria, with recognized and perfectly complementary expertise in 2D transistor theory and (nano-) fabrication will conduct systematic and exploratory research on MoS2 transistors and address the following objectives: Exploration of the scaling behavior of MoS2 FETs by thorough and comprehensive in-depth experimental and theoretical studies. Demonstration of MoS2 top-gate transistors with sub-10 nm gate lengths. Critical assessment of the prospects of ultimately scaled single- and multilayer MoS2 FETs considering processing constraints, switching speeds and non-idealities such as charge-trapping related issues. Assessment of p-type operation potential of MoS2 FETs. The partners will utilize state-of-the-art nanofabrication technology to explore the scaling limits of MoS2 FETs. Extensive work on device theory and simulation will be performed to get better insights in the physics and in the performance and scaling limits of TMD MOSFETs. The theoretical work will be closely linked to the experiments and be used to elaborate suitable designs for MoS2 FETs, taking into account the specifics of the processing environment as well as non-idealities such as charge trapping effects. Complete process flows for ultra-scaled MoS2 FETs will be established, including modules for gate dielectric deposition, boron nitride encapsulation and Ohmic contact formation. The resulting range of test structures and transistors from chemical vapor deposited films, including high frequency transistors for extracting switching delays, will undergo thorough analysis and characterization whose results, in turn, will be fed back to the theoretical work. The project will result in significant enhancements of the understanding of the physics, the scaling behavior and the process integration of MoS2 FETs and in a sound assessment of their merits and drawbacks.

For more than half a century, the progress in microelectronics has been described by Moore's law, which predicts a doubling of the number of transistors on a chip every 18 months and thus exponential growth, which is highly beneficial for economic and performance reasons. Despite many premature claims that Moore's law is at an end, according to the industry's roadmap scaling will continue during the next decade. A serious problem which results from these scaling efforts is that the thicknesses of the involved layers are approaching atomic dimensions, which makes further scaling difficult. For example, the most important microelectronic device is the field effect transistor (FET). In these FETs, a controlling gate voltage is applied over an insulator to modulate the electron concentration in the semiconducting channel, thereby allowing or forbidding current flow. Ideally, this insulator should block currents completely. However, the insulating layer was the first to hit atomic dimensions already around the year 2000. At that time, the insulators would have to be physically too thin to block currents, around 1nm, which would then lead to significant energy losses. To circumvent this problem, so called high-k insulators were introduced, which allowed for physically thicker layers while maintaining the control of the gate over the channel. The next problem is the thickness of the semiconducting channel layer: in order for the gate to exert full control over the channel, the channel thickness will have to be scaled below 5nm. Unfortunately, the conventionally used 3D semiconductors, like silicon, become very slow when the layer is made so thin. As a promising solution to this problem, 2D semiconductors have been extensively researched during the past decade. These materials have strong covalent bonds only along a plane and these thin layers are held together by weak van der Waals forces. A very important example is Molybdenum Disulfide, which is an emerging semiconducting material that has been previously used as a dry lubricant exactly because of these week van der Waals forces holding the layers together. With these 2D semiconductors ultra small devices can be built and exploration of this scaling process was the initial goal of the project. However, following some initial experiments, we realized that simply scaling the channel length resulted in very unsatisfactory device behavior. The reason for this turned out be related to the fact that 2D semiconductors cannot be simply used to replace silicon, as they form terrible interfaces to conventionally used insulators. While looking for alternatives we came across Calcium Fluoride, which is an ionic crystal with inert surfaces that can form clean van der Waals interfaces to 2D semiconductors. Initial experiments demonstrated the high quality of these devices and the versatility of Fluorides for 2D electronics.