Defect-Based Modeling of SiC Devices

Silicon carbide (SiC) has a number of unique properties such as a wide band gap, higher breakdown electric field than silicon, good thermal conductivity, high saturation velocity, and a reasonable bulk mobility. Additionally, SiC can grow a native oxide, thereby enabling its use in metal-oxide- semiconductor devices. All these properties make it an excellent candidate for power electronics. Nevertheless, wide commercialization of SiC is hindered by its surface/channel mobility which is substantially lower than that of the bulk material. This mobility reduction is attributed to a high concentration of defects at the SiC/SiO2 interface. These defects are also responsible for a large number of other detrimental phenomena such as the hysteresis seen in current-voltage characteristics, bias temperature instability (BTI), and hot-carrier degradation (HCD). Therefore, proper understanding and modeling of defects in the SiC/SiO2 system is crucial not only for mitigating reliability issues but highly required to realize the entire potential of non-stressed transistors. As a result, comprehensive modeling of non-stressed SiC transistors and reliability phenomena in these devices should be based on a consistent set of microscopic defect physics. As such, the primary goal of this project is to develop and validate a physics-based modeling framework which self-consistently considers all these parasitic effects as a response of interface and oxide defects/precursors which can be charged/activated by different driving forces. We expect that oxide traps are responsible for the temperature behavior and the hysteresis of current- voltage characteristics as well as for BTI. Therefore, these phenomena will be tackled consistently. Nevertheless, a possible contribution of pre-existing interface traps will also be checked. The interface traps will be modeled using Shockley-Read-Hall theory, while oxide traps will be described within the nonradiative multiphonon four states model. The strategy to distinguish between these traps relies on different behavior of their capture/emission times. As for HCD, in SiC transistors apparently it has two main contributions, i.e. interface trap generation and charging/discharging of oxide traps. The interplay of these mechanisms will be carefully analyzed and defect properties extracted. This extraction will be performed during optimization of the model parameters and using the characterization technique based on the analysis of capture/emission times of the defects. The defect properties obtained using these two methods will be compared against each other and with results of ab initio calculations. This defect-centric framework will ensure a comprehensive description of degradation mechanisms in SiC devices, thereby making it suitable for predictive reliability simulations. Furthermore, the information on the defect properties will be of great importance for applied physics, material science, and electrical engineering. The obtained results will be disseminated to the scientific community and the model will be made available through the software release channels of the host institute.

Silicon carbide's (SiC) rather unique properties, including its wide band gap, relatively high breakdown electric field, high saturation velocity, and a relatively high bulk mobility, make it an appealing choice for a wide range of applications, particularly in the field of high-power electronics. Its ability to grow native oxide with ostensibly a relatively low density of defects allows for the development of metal-oxide-semiconductor devices based on it. However, widespread development and commercialization of such devices has not been achieved due to various unresolved issues. Although charge transport in bulk SiC is extremely good, this does not translate to devices that are constructed from it. This effect is attributed to a persistently high concentration of defects at the SiC/SiO2 interface. These defects are also thought to be responsible for various other detrimental phenomena, such as the current-voltage (I-V) hysteresis, bias temperature instability (BTI), as well as hot-carrier degradation (HCD). The international technology roadmap for semiconductors (ITRS) lists both BTI and HCD among the most difficult challenges facing the industry which needs to be properly understood and modeled. Although extensive experimental and theoretical studies on these phenomena have been performed, there are still open issues in understanding the nature and behavior of defects contributing to BTI and HCD. While progress has been made in understanding these issues in Si-based devices, both separately and in conjunction with each other, the same cannot be said for SiC-based devices. A comprehensive model of SiC devices incorporating a consistent set of microscopic defect physics would be extremely desirable to develop and design novel, reliable SiC-based devices. The primary goal of this project was to develop and validate such a physics-based modeling framework that considers the effects of interface and oxide defects. Throughout operation of a device, these traps can be charged and discharged, thus affecting the device's electrostatics and ultimately its operating behavior. A combination of technology computer-aided design (TCAD) and atomistic simulations were used to develop a simulation framework that can properly describe the aforementioned effects in SiC-based devices. By extending existing models and simulation codes, we were able to reproduce the behavior of aforementioned issues; e.g. the hysteresis present in pristine SiC-based devices. Our developed defect-centric framework ensures a comprehensive description of degradation mechanisms in SiC devices, thereby making it suitable for predictive reliability simulations. Obtained results were disseminated to the scientific community via appropriate channels. All these important results have been published as high-impact papers as well as conference contributions.