Secure and Efficient Isogeny-based Cryptography in Hardware

Isogeny-based cryptography is a relatively new field of research. In recent years, isogeny problems have been used to construct novel cryptographic schemes such as post-quantum key agreement and signature and verifiable delay functions (VDF). Isogeny-based post-quantum public-key schemes typically have very small public keys and bandwidth compared to other mathematical classes of post-quantum schemes. Despite all these attractive features, a significant problem is that isogeny-based public-key schemes are very slow. Improving the speed of isogeny-based signature schemes and their secure and efficient realizations on computing platforms are fundamental research problems that we must address to make isogeny- based cryptography practical. Furthermore, investigating speed-up techniques for isogeny-based VDFs through custom hardware accelerators is crucial for their security analysis and deployment in the public domain. This project will research efficient hardware architecture design methods for isogeny-based cryptographic schemes and analyze their physical security.