Ensuring Robustness in Low-Power Asynchronous Circuits (ENROL)

Currently, virtually all reasonably complex digital circuits, such as microprocessors, have all their internal operational sequences controlled by a rigid clock, i.e. these circuits operate synchronous. An alternative design paradigm, namely asynchronous design, when suitably optimized, offers the potential for realizing the same functionality with higher energy efficiency, higher performance and higher robustness. The project ENROL is dedicated to the latter aspect, namely the question how far asynchronous designs are indeed more robust than synchronous ones, in terms of being more tolerant to external interferences or sub-optimal operating conditions. To this end, in a first step a formal model shall be elaborated for the fault-free behavior of asynchronous circuits designed following the most relevant existing asynchronous approaches. In a next step all possible fault effects shall be expressed in that model, classified and associated with their respective probabilities. For those faults that turn out to be finally tolerated, the mechanisms underlying this tolerance shall be explored. The results thus obtained shall be compared with those for comparable synchronous circuits to give evidence for the hypothesized higher robustness of asynchronous circuits; the differences shall be quantified by means of suitable metrics. In this process, theoretical considerations will be accompanied by comprehensive simulation studies and experimental measurements for circuits whose design is part of the project as well. Based on the thorough understanding of the fault effects and the inherent fault tolerance mechanisms, well directed modifications to and extensions of the asynchronous circuits and concepts can be devised to further enhance their robustness. Here, the available concepts range from technological enhancements (transistor geometry and placement) over changes in the circuit towards coding methods. While fault-tolerance approaches for asynchronous designs do exist in the literature already, the systematic treatment of the topic from modelling to experiment, covering all relevant design asynchronous design paradigms, and directly comparing all alternatives, clearly represents a contribution to the state of the art. The results of ENROL will allow to give evidence for and to better leverage the robustness benefits of asynchronous design. This could make the latter more attractive for critical applications where designers would as well appreciate the other advantages like energy efficiency or higher performance. So on the long run ENROL will contribute to constructing fast and energy-efficient computers that yet work reliable under faults and sub-optimal conditions.

Research project "Ensuring Robustness in Low-Power Asynchronous Circuits (ENROL)" Summary Computers are increasingly entrusted with applications where their failure can have fatal consequences. Therefore, in these use cases, they must be able to provide correct results even when affected by disturbances like electromagnetic fields or radiation - in other words, they must be fault tolerant. For conventional synchronous computers there are numerous established methods to attain fault tolerance. Relatively few solutions, however, are available for asynchronous computers. While the traditional synchronous computers always operate with the same constant speed, dictated by their clock frequency, asynchronous computers dynamically and naturally adapt their speed of operation to the requirements as well as the operating conditions. This makes them, by their principle, more robust against disturbances that affect their temporal behavior. In addition, this creates their potential to operate with higher energy efficiency. The same principles are also used in "neuromorphic" computers that try to imitate the function of the brain, which are currently often found in the context of artificial intelligence. The main aim of the project ENROL was the systematic exploration of the fault sensitivity of asynchronous computers, and, building on that, the elaboration of mechanisms to improve their fault tolerance. The research team could pinpoint, in which way the robustness of basic building blocks of asynchronous computers depends on the workload, where particularly sensitive regions are, and at which times, relative to the program flow, the sensitivity is specifically high. The fault-tolerance enhancement methods derived from this are therefore precisely targeted and create little overhead. The latter is not only important because it is a prerequisite for retaining the asynchronous computers' energy efficiency, but also because each component that is added can again be affected by a disturbance. To provide evidence for the improvements obtained, billions of artificially created disturbances were inserted into asynchronous computers, or their constituent building blocks, respectively, in the course of simulation experiments. Their effects were studied, once before and once after the introduction of the enhancement methods. The improvements thus observed were dependent on the specific case, but in general considerable. These comprehensive experiments, in turn, were only possible after the research team had created a suitable infrastructure that facilitates the efficient study of the behavior under varying function block, workload, operating conditions and disturbance. In the elaboration of the results, the research team has been in cooperation with other researchers from Germany, France and the US. In summary, the project ENROL has thus made an important contribution to make the employment of asynchronous computers in safety-relevant applications more attractive, therefore allowing to better leverage their potentials there.