Studies of Ionizing Radiation Effects in NanoScale CMOS

There are specific cases where electronic devices and instruments have to operate in a severe environment of ionizing radiation, like X- and gamma rays, alpha or beta radiation. This is the case for space instruments, some medical applications as well as in high energy physics experiments, like CERN colliders with extreme radiation intensity. The ionizing radiation causes damage to transistors, changing their properties. Integrated circuits that are designed to perform various detection, computing, communication and power management functions are composed of thousands or millions of transistors become unreliable. The damage mechanisms of integrated circuits along with mitigation techniques have been studied over the last four decades and their understanding has much progressed. However in the meantime also technology progress is ongoing, the transistor feature size is being scaled down and with each new process node technological processes are changing and new materials have to be incorporated. All that in order to achieve even higher speed electronic systems, highly integrated, low power, affordable and reliable. With these changes in structure and composition also the radiation effects are different. They are dominated by second order effects due to ultra-small dimensions. The critical barrier due to new material compounds happens between 40 and 65 nanometer process nodes, which defines the smallest channel length of transistor in a given process node. This is around the size of the diameter of the flu virus. In this project a group of researchers is going to focus on the technologies at this border and below. The individual transistors will be measured before and after X-rays stress. These measurements will involve several techniques of electrical characterization and are meant to identify evolution of the electrical properties under exposure to X-rays also in combination with other environmental conditions, like electric field and temperature. The transistor behaviour has to be modelled in order to understand how the radiation damage of individual transistor influences operation of the entire integrated circuit composed of thousands or millions of transistors. This functional effect on the behaviour of the integrated circuit can be then verified by means of computer simulations. The possibility of early identification of potential problems is particularly valuable, since mitigation strategies can be applied at the circuit level. That is, even if individual transistors experience damage due to ionizing radiation, the circuit architecture can be possibly designed in a way to cancel-out the shift of the characteristics. Finally the radiation damage evaluation is also important for prediction of the lifetime of integrated circuit as long as details of the environmental stress are known a priori.

The extreme levels of ionizing radiation in high-energy physics experiments, such as the Large Hadron Collider (LHC) at CERN, can result in severe damage to electronic components and lead to circuit malfunctions. The project investigated how exposure to X-rays influences the characteristics of nanoscale transistors. Transistors are the fundamental building blocks of integrated circuits (ICs), whereas detectors monitoring particle interactions in accelerators are equipped with dedicated ICs. The relevance is even broader, as further families of custom ICs are used for data processing, data transmission, and electrical power management. For any of these ICs, the prediction of circuit failure due to exposure to ionizing radiation starts at a profound understanding of how the individual transistors degrade under given stress conditions. This is the first step to ensure the long lifetime of an integrated circuit. This reliability aspect is essential in a harsh environment, such as a high-energy physics experiment, where replacing a damaged electronic component would be complicated or sometimes impossible. The SIRENS project focused on 28 nm and 40 nm CMOS technologies of a smaller feature size than the 65 nm CMOS process node used for the electronic readout of many detectors in the LHC upgrade planned until 2030. Therefore, the relevance reaches beyond the state-of-the-art detectors: the knowledge gained from the project is valuable for the ICs used in the future high-energy physics instrumentation, such as the Future Circular Collider (FCC). With the IC process node downscaling, transistors become more robust to ionizing radiation stress and can withstand much higher exposure. What becomes critical are the microscopic differences, observed, e.g., as the electronic noise. It means that the number of charge carriers (in semiconductors, electrons or holes) in a transistor is not constant but fluctuates because of the so-called "charge traps". For example, if one electron is trapped, it will make more of a difference for a small-area transistor. Importantly, the ionizing radiation leads to the formation of charge traps or the evolution of the existing ones. In this project, next to experimental observations, a multi-physics model was developed to model how the current through a transistor changes depending on the location of a charge trap. Why are these results significant? They help assess the stability of circuit parameters, e.g., circuits that read out information from the particle detectors. As the charge trapping effects are also happening frequently under normal conditions, the statistically significant project findings are also of value for scaled ICs for other applications, where radiation stress is not a concern.