Analysis & Modeling of Single-Event-Transients in VLSI Chips

Due to the steadily decreasing feature sizes of modern VLSI circuits, which are in the nanometer range (< 100 nm) nowadays, single-event effects (SEEs) are increasingly dominating the fault rate of VLSI circuits. SEEs occur when junctions of transistors are hit by ionized particles. Such particles primarily originate in high-energy cosmic radiation, affecting a chip either directly (at high altitudes, i.e., in space and aerospace) or indirectly, via interaction with the atmosphere. The primary concern in modern VLSI circuits are transient SEEs: An ionized particle deposits charge along its track, which in turn can cause a single-event transient (SET) signal pulse (0.1- 1 ns range). If a sufficiently strong SET propagates to a storage element, it can be latched, thereby producing a single-event upset (SEU). Robust circuit design, in particular, for critical applications, hence needs models that accurately describe SETs/SEUs and are easy and efficient to use at early design stages. Such models both allow (a) to assess the radiation tolerance of different architectural designs and hardening techniques and (b) to estimate the final error rate of a circuit. The preferred method to accomplish this is simulation-based fault injection at the (analog) electrical level: Typically, a Spice model of the circuit (derived automatically from the design using technology libraries) is augmented with Spice models that simulate SET generation in critical parts of the circuit. The most commonly approach here is single-ended injection of a double-exponential current into the drain of a transistor. Obviously, the suitability of this method for validating the effectiveness of radiation-hardening measures and predicting soft-error rates stands or falls with the availability of accurate Spice models for SET generation: If it fails to cover important scenarios, one might e.g. overlook situations where radiation-hardening fails. Unfortunately, there is evidence that standard double-exponential Spice models are susceptible to such problems, with respect to several aspects: (1) Inadequate model structure, (2) calibration of model parameters, and (3) SEEs affecting multiple transistors or gates. The latter necessitates the consideration of the layout in the Spice model for the SET. Any attempt to developing Spice models that accurately model SET generation (including the above complications) in nanometer VLSI circuits requires a combination of both (a) a detailed understanding of the physical/electrical processes involved and (b) a comprehensive experimental evaluation of SET pulses arising in real circuits. The project EASET is devoted to this purpose: It will use results from accurate analog SET measurements in carefully designed measurement ASICs under micro-beam irradiation to (i) guide the development and (ii) calibrate detailed 3D physical/hybrid TCAD simulation models. The latter is a very powerful means for researching the SET generation process and its parameters in VLSI circuits, and thus also the appropriate basis for developing and validating novel SET generation Spice models for complex nanometer VLSI circuits, which are the primary intended outcome of the project. The measurement ASICs will include on the one hand the circuits under test, e.g. circuits based on basic combinational and sequential logic and possibly some other topologies like ring oscillators. On the other hand the ASICs will include high speed analog measurement amplifiers which must have minimum influence on the investigated circuit nodes, and they have to include high speed analog 50O-output drivers. Additional analog high speed multiplexers are necessary due to the large number of investigated circuit nodes. Consequently, EASET not only addresses interesting fundamental research questions, but also provides results that are relevant in practice. The required competence is ensured by running it as a joint project between the Institut für Technische Informatik and the Institute of Electrodynamics, Microwave and Circuit Engineering at TU Wien, which also includes external collaborations with radiation physics experts e.g. at the GSI in Darmstadt and the PTB in Braunschweig.

Malfunction of computers caused by radiation particle hits has always been a concern in environments where such particles are abundant and have high energies, like in space. However, in modern computers the sizes of the chip-internal structures are so small that they are susceptible to particles with lower energy and those are frequent on earth as well, in our immediate environment. Unless we take measures to mitigate or tolerate errors introduced into a computer (or any modern electronics in general), future chip generations will no more work reliably. Unfortunately, the fault mitigation and fault-tolerance techniques already known from space technology are either too costly for everyday applications, or not effective for those types of errors that occur in modern chips with their small structures, like e.g. one particle causing two errors at the same time in two neighboring circuit elements. Therefore, it is of utmost importance to attain a better understanding of the effects of particle hits in modern chips to come up with radiation tolerance techniques that are affordable and effective at the same time.This was exactly the dedication of the EASET project. We have developed and fabricated several digital microchips in modern technologies, and exposed them to radiation to observe the effects. The unique thing about these experiments was that (a) we used microbeams as radiation sources, where the radiation (location of particle hit, type, rate and energy of particles etc.) can be very well controlled, and (b) our chips were equipped with internal infrastructure blocks that support the analysis of the particle effects. One type of such infrastructure was an amplifier that allowed us to directly watch the signal shapes resulting from the particle hits and even correlate them with the causing particle properties. Another type of infrastructure allowed us to generate statistics about the effects of particle hits on the chip. The development of these infrastructure blocks was a major challenge in the project.The analysis of the measurement data obtained from these experiments allowed us developing a better understanding about the dependences of the particle effects on several parameters, like, e.g., location or angle of particle incidence. With this knowledge we were able to improve the accuracy of simulation models that can be used to study the effects of particle hits in a more flexible and comprehensive way than by physical experiments. While the improvement of the simulation model was probably the most important project result, and forms a vital stepping stone for elaborating efficient radiation tolerance methods, we elaborated numerous other results like observation of effects that have so far not been reported, or innovative fault-tolerance techniques.